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My mistake. I meant to say something nicer. Log in to see images!
Have this instead>>>>>>>>>>>>
o *INC A and DEC A.
o *BRA relative. Unconditional branch.
o *BIT #immediate. The CMOS chips also have BIT absolute,X and BIT zeropage,X.
o STX absolute,Y and STY absolute,X. How come LDX and LDY can use these addressing modes, but the matching store instructions can’t?
o SEV. Set overflow bit. Probably not really useful, but you can set and clear all of the other status bits, and there *is* a CLV.
o Personally, I’d also like to have “Clear A” and “Test A” instructions. These would be twice as fast and half as big as LDA #0 and CMP #0. Ironically, the CMOS chips have an STZ (Store Zero) instruction which can clear a memory location, but still can’t clear the Acgreat timesulator.
o I’d also like to have BSR relative. A subroutine call that’s relocatable.
*Fixed in the CMOS versions (65C02, 65C102, etc.) |
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Posted On: 01/14/2010 4:57PM | View aSh-gangSTA-685's Profile | # |